During the conception of an integrated circuit comprising millions of transistors, a key phase of the design process is the operation known as “place and route”. During this operation, a GDS (graphic database system) file of the circuit design is generated by a dedicated conception tool prior to fabrication. The conception tool first places the cells of the circuit design on the available surface of the integrated circuit, and then a routing algorithm is applied that interconnects the cells of the circuit design in order to create a circuit layout.
3D circuits, in which cells are positioned on multiple stacked levels interconnected by 3D vias, provide many advantages in terms of circuit compactness and performance. For example, monolithic 3D transistor technology, also known as sequential 3D and CoolCube™, involves the fabrication of a plurality of layers of transistors as a single block. In particular, two or more layers or tiers of transistors are formed sequentially, and interconnected by vertical 3D vias. For example, this technology is described in more detail in the publication by P. Batude et al. entitled “3D sequential integration opportunities and technology optimization”, IEEE International Interconnect Technology Conference, 2014, pages 373-376. An advantage of monolithic 3D technology with respect to other 3D technologies is that the process allows a high density of interconnections (small size and spacing of the vias) when compared with TSVs (Through-Silicon-Vias) or face-to-face contact (copper to copper). Furthermore, 3D fabrication processes that involve stacking two or more integrated circuits suffer from problems of alignment, contrary to the monolithic 3D approach in which the device is fabricated sequentially.
A problem for 3D circuit design is that existing software tools implementing place and route have been developed for 2D circuits, and are not compatible with the generation of high-density 3D circuit designs. Furthermore, creating a new design tool configured for 3D circuit design would be time consuming and costly.
There is this a need in the art for a circuit design method and device permitting the conception of 3D circuits having relatively high density.